Many computer systems, including personal computers (PCs), employ virtual memory. Virtual memory is the simulation of a uniformly addressable computational memory large enough to accommodate all instantiations of a program on all configurations of a computer system. Virtual memory provides a uniform address format and addressing protocol that is independent of the sizes of the memory levels in the system and the number of processing elements. The set of addresses that a processor can generate as it executes a program is called the virtual address space of a program. The set of addresses recognized by a memory device of the computer system is called the memory space. A buffer of virtual memory could appear to be contiguous in the virtual memory space although the underlying physical memory in the memory space is non-contiguous (i.e., the blocks of physical memory allocated for the buffer is scattered randomly in the virtual memory space).
The mapping of processor-generated addresses in the virtual address space to memory-recognizable addresses in the memory space is typically carried out by a dynamic address translator (DAT) interposed between a processor and a memory system. The DAT makes address translation transparent to the programmer. Addressing invariance with respect to changes in the computer system's configuration or the distribution of data among memory elements is achieved by allowing the operating system of the computer system to change mapping tables during a program's execution. The system state is dynamically reflected in the mapping of the virtual address space to the memory space, rather than in the program itself.
The mapping from the virtual address space to the memory space is usually stored in a direct lookup mapping table for fast retrieval and update. Both the virtual address space and the memory space are divided into blocks. In a mapping scheme called paging, the blocks of the virtual address space are called pages, and the blocks of the memory space are called page frames. The mapping table specifies the page frame in which each page is stored. A virtual address generated by the processor is partitioned into the high-order bits which function as a page number and the low-order bits which function as a byte offset within the page. Address translation is the substitution of the page frame number for the page number.
A small associative memory called a translation lookaside buffer (TLB) is often included inside the translator mechanism in conjunction with a processor. The TLB holds the mapping table. Each TLB cell contains a page address translation entry of the mapping table which is accessed much faster than an entry stored in the main memory for the computer system. To perform an address translation, the translator interrogates the TLB. If an entry is not found in the TLB to assist in the translation, the translator must obtain the mapping from main memory. The new entry fetched from main memory typically replaces the least recently used entry in the TLB.
In some situations, a peripheral processor or device (such as an audio processing unit or graphics accelerator processor) must access main memory to obtain data necessary for peripheral processing. The peripheral processor may be passed a virtual address of the start of the data in main memory by the central processing unit (CPU) of the computer system. The peripheral processor performs the address translation function to obtain the address in the memory space where the data physically resides, and then fetches the data. If the page address translation entries are stored on the peripheral device, access time is minimized but the local memory required for the entries could be very large. If the page address translation entries are stored in main memory, additional memory is not needed on the peripheral device, but access time to the entries by the peripheral processor may become prohibitively slow.
FIG. 1 is a diagram of a prior art peripheral processing unit coupled to a main memory by a bus. On one side of a Bus 10 (such as a Peripheral Component Interconnect(PCI) Bus or a VL-Bus (VLB), a CPU 12 interacts with a Main Memory 14. On the other side of the Bus is a Peripheral Processing Unit 16 including a Peripheral Processor 18. The Peripheral Processor is generally coupled to one or more peripheral devices (not shown). The Peripheral Processor is an audio data processing subsystem commonly known as an audio accelerator, a display processing subsystem such as a graphics accelerator, or other subsystem providing predetermined capabilities. The Peripheral Processor uses a Dynamic Address Translator 20 to translate a virtual page address (in the virtual address space) into a real page address (in the memory space). The Translation Lookaside Buffer 22 holds the most recently used page address translation entries.
The storage needed on the Peripheral Processor for the page address translation entries in many cases is very large and expensive to implement. In some implementations, only selected page address translation entries are cached in the Translation Lookaside Buffer 22 and the majority of the page address translation entries are stored in Main Memory 14. Whenever the Dynamic Address Translator needs to translate a given page address that is not currently stored in the Translation Lookaside Buffer, the peripheral-side hardware (i.e., an audio or graphics accelerator) pauses the translation function, fetches the required entry from the Main Memory 14, and then continues with peripheral processing by completing the translation function and fetching the desired data from the Main Memory at the computed physical address. However, this activity requires an extra read operation over the Bus 10 to get the desired page address translation entry for each page of data. The time delay incurred by the Peripheral Processor 18 while waiting for the page address translation entry to be delivered can be substantial, thereby negatively affecting overall system performance. For peripheral processing units such as audio or graphics accelerators, this increased latency for page address translation entry access results in unacceptable performance for updating computer displays or outputting audio signals through a loudspeaker to a user.